Generally, ADC is an electronic circuit which converts the continuous time, continuous amplitude signal into discrete amplitude (quantization) and discrete time samples (sampling) which are suitable for processing further using digital logic and/or computer software. Depending on whether a clock is supplied to the ADC and digital samples are obtained in synchronization with the edges of the clock, ADCs can be broadly classified as (a) synchronous ADCs and (b) asynchronous ADCs. The quality of the ADC conversion is usually measured in terms of effective number of bits (ENOB) or Signal-to-Noise and Distortion Ratio (SNDR) for the given (synchronous) output sampling rate. This ENOB/SNDR can be different from another unit used to measure the output sample quality called the resolution which indicates the number of bits used to represent the output samples.
The input signal range that the ADC can handle is usually measured in terms of the signal swing (e.g., in Volts peak-to-peak (Vpp)) within which the ADC converts the analog signal into digital samples which are linearly related to the input signal amplitude at the sampling time instants. This input dynamic range may be specified in terms of the signal swing such as +/−0.5 V (1 Vpp), +/−1 V (2Vpp), etc.
In prior art, ADC exists in multiple architectures such as (a) Pipeline ADC, (b) Successive Approximation (SAR) ADC, (c) Delta-Sigma ADC, (d) Flash ADC, etc. All the above ADCs are synchronous ADCs where the sampling is done in synchronization with one or both of the edges of the clock supplied to the ADC. Different ADC architectures may have different conversion time requirements. Hence, a sample and hold (S-H) is used typically to hold the information of the continuous time signal at the time of sampling and then converted to digital output. The digital outputs also may be sent in synchronization with the input clock. The digital output maybe sent either serially or in parallel bus. In contrast, the asynchronous ADCs may not sample the continuous time signal in synchronization with the input clock. Moreover, the output sampling rate may not be integer multiples of the maximum frequency of the input signal.
FIG. 1. shows the block diagram of the prior art ADCs. The anti-aliasing filter is also used to limit the swing of the input signal to the ADC.
Generally, in the prior art, the input signal swing is limited to less than the maximum input signal swing by the anti-aliasing filter or driver which precedes the ADC. When the input signal exceeds the desired range, the anti-aliasing filter output will be compressed (that is, a soft-clipping of the voltage levels beyond the range supported by the filter or ADC) and hence ADC output digital representation codes will be clipped to a particular code value accordingly.
In case that anti-aliasing filter or driver did not enforce the input signal swing, the output of the ADC will be clipped to the maximum code which corresponds to the maximum input signal amplitude.
Therefore, there is a need in the art as understood by the present inventors to recover the clipped signal in a manner that addresses at least some of the concerns of the usage of the prior art.